The present invention relates generally to improvements in MOS (metal-oxide-semiconductor) memories and, more particularly, to a shared sense amplifier arrangement for sensing the logic state of a memory cell.
In typical MOS memories, digital data is stored in a matrix of memory cells. Each cell includes a capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state. A large number of such memory cells are typically associated with each of the memory's bit lines. A number of dummy cells are also included in the memory. These dummy cells have dummy capacitors which are precharged to reference voltage levels. To sense the state of an addressed memory cell, the charge of the memory's cell capacitor is dumped on a first bit line and the charge on the dummy cell's capacitor is dumped on a second bit line. The resultant difference in voltage on the two bit lines is sensed by a sense amplifier and used as an indication of whether the memory cell is in a logic 1 or a logic 0 state.
In the prior art, a sense amplifier is typically positioned between and coupled to two pairs of bit lines. In addition, the sense amplifier is constructed to sense the voltage difference between diagonally opposite bit lines, i.e., a bit line from one pair on one side of the amplifier and a bit line from the other pair on the other side of the amplifier. One of the sensed bit lines is normally coupled to an accessed memory cell and the other sensed bit line is coupled to a dummy cell so that the sense amplifier can latch in a state representative of the logic level associated with the accessed memory cell. Because the bit lines on one side of the sense amplifier are typically coupled to input/output buss lines, the latter bit lines are used as conductive paths for coupling the latched state of the sense amplifier to the input/output buss lines. This facility for easily reading the latched state of the sense amplifier is a prime reason for the above-mentioned arrangement.
The problem with the above-described arrangement is that a bit line and its diagonally opposite bit line, both of which are being sensed, are not physically near each other. Hence, any noise which affects one of the sensed bit lines does not affect the other sensed bit line in the same manner. The resulting noise differential on the sensed bit lines inhibits the sense amplifier from accurately sensing the voltage level of the accessed memory cell.
For the foregoing reason, conventional sense amplifier arrangements become increasingly unreliable as the noise on a bit line increases.